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[ak4711] rev. 0.4 2011/07 - 1 - features audio section ? thd+n: ? 92db (@2vrms) ? dynamic range: 96db (@2vrms, a-weighted) ? full differential or single-ended input for decoder dac ? stereo output for tv scart and cinch (2vrms) ? ground-referenced output eliminates dc-blocking capacitor and mute circuit video section ? integrated lpf sd: ?40db@27mhz hd: ?40db@74.25mhz or 54mhz or 27mhz selectable ? 6db gain for outputs ? 5ch 75ohm driver 4ch for scart: cvbs/y, r/c, g, b 1ch for cinch: cvbs ? y/pb/pr option (to 6mhz) low-power standby scart pin#16(fast blanking), pin#8( slow blanking) output control power supply ? 3.3v+/ ? 5% and 12v+/ ? 5% ? low power dissipation / low power standby mode package ? 36pin qfn (0.4mm pitch) low power single scart driver with hd fil ak4711 = preliminary =
[ak4711] rev. 0.4 2011/07 - 2 - block diagram tvoutl tvoutr ai nl+ ai nl- ai nr- ai nr+ mono scl sda register control pdn vd1 amp vss1 volume -6db to +24db (3db/step) cp cn vee vss2 charge pump vd2 tv scart cinch audio audio block tvvout tvrc tvg tvb rcavout hdy hdpb hdpr 6db encv ency encrc encc encg encb ( typical connection ) tv scart cinch vi deo ( typical connection ) vvd hdvvd vss3 6db 6db 6db 6db 6:8 selector enc cvbs/y enc y enc r/c/pr enc c enc g/cvbs enc b/pb 6db 6db 6db hd video video block tvfb 6db 0v 1.25v tvsb 0/ 6/ 12v tv scart ( typical connection ) vp video blanking block
[ak4711] rev. 0.4 2011/07 - 3 - ordering guide AK4711EN -10 +70 c 36pin qfn (0.4mm pitch) akd4711 evaluation board for ak4711 pin layout 36pin qfn (0.4mm pitch) 28 pdn 29 cn 30 cp 31 vss2 32 vd2 33 34 scl 35 sda 36 hdvdd 27 2 6 25 24 23 22 21 20 hdy 1 hdpr 2 hdpb 3 rcavout 4 vss3 5 tvvou t 6 tvfb 7 tvrc 8 tvg 9 17 16 15 14 13 12 11 10 vvd tvb to p v i e w 18 19 vee ak4711 encg encb encc enrc ency encv vp ainr+ a inr- tvoutl tvout r vd1 vss1 tvsb ainl+ ainl-
[ak4711] rev. 0.4 2011/07 - 4 - pin/function no. pin name i/o function 1 hdy o green/y output pin 2 hdpr o red/pr output pin 3 hdpb o blue/pb output pin 4 rcavout o composite/luminance output pin for rca 5 vss3 - video ground pin , 0v 6 tvvout o composite/luminance output pin for tv 7 tvfb o fast blanking output pin for tv 8 tvrc o red/chrominance output pin for tv 9 tvg o green output pin for tv 10 tvb o blue output pin for tv 11 vvd - video power supply pin: 3.13v ~ 3.47v normally connected to vss3 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. 12 encb i blue input pin for encoder 13 encg i green input pin for encoder 14 encrc i red/chrominance input pin #1 for encoder 15 encc i chrominance input pin #2 for encoder 16 encv i composite/luminance input pin #1 for encoder 17 ency i composite/luminance input pin #2 for encoder 18 vp - blanking power supply pin, 10.8v ~ 13.2v the vp pin must connect to power supply through 10ohm resistor with 0.1 f ceramic capacitor in parallel with a 1 f electrolytic capacitor to vss1. 19 tvsb o slow blanking output pin for tv a 470ohm 5% resistor must be connected between the tvsb pin and scart connector. 20 vss1 - audio ground pin , 0v 21 vd1 - audio power supply pin: 3.13v ~ 3.47v normally connected to vss1 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. 22 tvoutr o rch anal og output pin #2 23 tvoutl o lch analog output pin #2 24 ainrn i rch negative analog input pin 25 ainrp i rch positive analog input pin 26 ainln i lch negative analog input pin 27 ainlp i lch positive analog input pin 28 vee o negative voltage output pin connect to vss2 with a 1.0 f capacitor that should have the low esr ( equivalent series resistance ) over all temperature range. when this capacitor has the polarity, the positive polarity pin should be connect ed to the vss2 pin. non polarity capacitors can also be used. 29 cn i negative charge pump capacitor terminal pin connect to cp with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature ra nge. when this capacitor has the polarity, the positive polarity pin should be connected to the cp pin. non polarity capacitors can also be used. 30 cp i positive charge pump capacitor terminal pin connect to cn with a 1.0 f capacitor that should have the low esr (equivalent series resistance) over all temperature ra nge. when this capacitor has the polarity, the positive polarity pin should be connected to the cp pin. non polarity capacitors can also be used. 31 vss2 - charge pump ground pin , 0v 32 vd2 - charge pump power supply pin: 3.13v ~ 3.47v
[ak4711] rev. 0.4 2011/07 - 5 - normally connected to vss2 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic cap. 33 scl i control data clock pin 34 sda i/o control data pin 35 pdn i power-down mode pin when at ?l?, the ak4711 is in the power-down mode and is held in reset. the ak4711 should always be reset upon power-up. 36 hdvvd - video power supply pin: 3.13v ~ 3.47v normally connected to vss3 with a 0.1 f ceramic capacitor in parallel with a 4.7 f electrolytic capacitor. note: all digital input pins should not be left floating.
[ak4711] rev. 0.4 2011/07 - 6 - absolute maximum ratings (vss1 =vss2 =vss3 = 0v; note 1 ) parameter symbol min max units power supply ( note 2 ) vd1 vd2 vvd hdvdd vp ? 0.3 -0.3 ? 0.3 ? 0.3 ? 0.3 4.0 4.0 4.0 4.0 14 v v v v v input current (any pins except for supplies) iin - 10 ma digital input voltage(pdn pin) vind1 ? 0.3 vvd+0.3 v digital input voltage(scl, sda pins) vind2 ? 0.3 4.0 v video input voltage vinv ? 0.3 vvd+0.3 v audio input voltage ( note 3 ) vina vee-0.3 vd1+0.3 v ambient operating temperature ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss1, vss2 and vss3 must be connected to the same analog ground plane. note 3. vee: vee pin voltage. the internal negative power supply generating circuit provides negative power supply(vee). the pdn pin and mute bit control operation mode as shown in table 2 and table 3 . mode vee pin voltage 0 full power-down 0v 1 mute 0v no video input 0v 2 normal operation video input -vd2+0.2v table 1. vee pin voltage warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
[ak4711] rev. 0.4 2011/07 - 7 - recommended operating conditions (vss1 =vss2 =vss3 = 0v; note 1 ) parameter symbol min typ max units power supply ( note 4 ) vd1 vd2 vvd hdvdd vp 3.13 3.13 3.13 3.13 10.8 3.3 3.3 3.3 3.3 12 3.47 3.47 3.47 3.47 13.2 v v v v v note 1. all voltages with respect to ground. note 4. vvd and hdvdd must be connected to the same voltage. *akm assumes no responsibility for the usage beyond recommended operating conditions in this datasheet. electrical characteristics (ta = 25 c; vp=12v, vd1=vd2=vvd=hdvvd= 3.3v) power supplies min typ max units power supply current normal operation (pdn = ?h?) ( note 5 ) vd1+vd2+vvd+hdvdd vp power-down mode (pdn = ?l?) ( note 6 ) vd1+vd2 vvd hdvdd vp 386 48 0 0 0 48 tbd tbd tbd tbd tbd tbd a a a a a a note 5. stby bit = ?0?, all video outputs active. no signal, no load for a/v switches. refer to table 3 . note 6. all digital inputs are held at vvd or vss3. no signal, no load for a/v switches. digital characteristics (ta = 25 c; vd1=vd2=vvd=hdvvd= 3.13 3.47v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vvd - - - - 30%vvd v v low-level output voltage (sda pin: iout= 3ma) vol - - 0.4 v input leakage current iin - - 10 a
[ak4711] rev. 0.4 2011/07 - 8 - analog characteristics (audio) (ta=25 c; vp=12v, vd1=vd2=vvd=hdvvd= 3.3v; signal frequency=1khz; measurement frequency=20hz 20khz; r l 4.5k ; 0db=2vrms output; volume =0db, unless otherwise specified) parameter min typ max units analog input: (ainl+/ainl-/ainr-/ainr+ pins) analog input characteristics input voltage (ain+) ? (ain ? ) ( note 7 ) 2.0 vrms input resistance (ainl+, ainr+ pins) 85 120 k input resistance (ainl-, ainr- pins) 85 120 - k stereo/mono output: (tvoutl/tvoutr pins) ( note 8 ) analog output characteristics volume step width tbd 3.0 tbd db thd+n (at 2vrms output, note 10, note 12 ) ? 92 tbd db dynamic rang ( ? 60db output, a-weighted, note 10 ) tbd 96 db s/n (a-weighted, note 10, note 14 ) tbd 96 db interchannel isolation ( note 10 , note 11 ) tbd 90 db interchannel gain mismatch ( note 10 , note 11 ) -0.5 0 +0.5 db dc offset ( note 13 ) -5 0 +5 mv gain drift - 200 - ppm/ c load resistance tvoutl/r 4.5 k load capacitance tvoutl/r 20 pf output voltage ( note 9 ) 1.8 2 2.2 vrms power supply rejection (psr) ( note 15 ) - 50 db note 7. f = 1khz, thd+n < -80db, gain = 0db(volume=0db) note 8. measured by audio precision system two cascade. note 9. the output level of the internal amp with volume should be less than 2vrms. note 10. analog in to tvout. path : ainl+/ ? tvoutl, ainr+/ ? tvoutr, volume=0db. at 2vrms single input, tdh+n is -91db (typ), on path ainl+ tvoutl, ainr+ tvoutr, volume=0db note 11. between tvoutl and tvoutr with analog inputs ainl+/ ? , ainl/r+/ ? , 1khz/0db. inter-channel crosstalk is -80db (typ), at 20hz~20khz other than 1khz. note 12. -79db (typ) referred to 0.5vrms output level at volume=+24db : path = ain+/- tvout. note 13. analog in to tvout. volume=0db path : ainl+/ ? tvoutl, ainr+/ ? tvoutr note 14. 82db (typ) referred to 0.5vrms output level at volume=+24db 84db (typ), referred to 0.5vrm output level at volume = +21db. : path = ain+/- tvout. note 15. the psr is applied to vd1 and vd2 with 1khz, 100mv.
[ak4711] rev. 0.4 2011/07 - 9 - analog characteristics (sd video) (ta = 25 c; vp = 12v, vd1=vd2= vvd=hdvvd= 3.3v ; unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.20 v r/g/b clamp voltage at output pin. 0.20 v pb/pr clamp voltage at output pin. 1.44 v chrominance bias voltage at output pin. 1.44 v gain input = 0.3vp-p, 100khz 5.5 6 6.5 db interchannel gain mismatch tvrc, tvg, tvb. input = 0.3vp-p, 100khz. -0.5 - 0.5 db frequency response input=0.3vp-p, c1=c2=0pf. 100khz to 6mhz. at 10mhz. at 27mhz. -1.0 -3 -40 0.5 -20 db db db group delay distortion at 4.43mhz with respect to 1mhz. 20 ns input impedance chrominance input (internally biased) tbd 100 - k input signal f = 100khz, maximum with distortion < 1.0%, gain = 6db. - - 1.25 vpp load resistance ( figure 1 ) 150 - - load capacitance c1 ( figure 1 ) c2 ( figure 1 ) 400 15 pf pf dynamic output signal f = 100khz, maximum with distortion < 1.0% - - 2.5 vpp y/c crosstalk f = 4.43mhz, 1vp-p input. among tvvout, tvrc and rcavout outputs. - ? 50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw = 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 0.6 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - 1.4 - degree video signal output 75 ohm 75 ohm max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
[ak4711] rev. 0.4 2011/07 - 10 - analog characteristics (hd video) (ta = 25 c; vp=12v, vd1=vd2=vvd=hdvvd= 3.3v , unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.20 v r/g/b clamp voltage at output pin. 0.20 v pb/pr clamp voltage at output pin. 1.44 v gain input=0.3vp-p, 100khz 5.5 6 6.5 db fl1/0,flpb1/0,flpr1/0= ?10? 100khz to 20mhz, at 30mhz. at 74.25mhz. -1.0 -2.5 -40 1.0 -25 db db db fl1/0,flpb1/0,flpr1/0= ?01? 100khz to 15mhz, at 54mhz. -1.0 -40 1.0 -25 db db frequency response input=0.3vp-p, c1=c2=0pf ( figure 1 ) fl1/0,flpb1/0,flpr1/0= ?00? 100khz to 6mhz, at 27mhz. -1.0 -40 0.5 -25 db db input signal f=100khz, distortion < 1.0%, gain=6db - - 1.25 vpp load resistance ( figure 1 ) 150 - - load capacitance c1 ( figure 1 ) c2 ( figure 1 ) 400 10 pf pf dynamic output signal f=100khz, distortion < 1.0% - - 2.5 vpp s/n reference level = 0.7vp-p, ccir 567 weighting. bw = 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. fl1/0, flpb1/0, flpr1/0= ?00? - +0.3 - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. fl1/0, flpb1/0, flpr1/0= ?00? - +0.6 - degree
[ak4711] rev. 0.4 2011/07 - 11 - switching characteristics (ta = 25 c; vp = 10.8 13.2v, vd1=vd2= vvd=hdvvd= 3.13 3.47v) parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 16 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf reset timing pdn pulse width ( note 17 ) tpd 150 ns note 16. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 17. the ak4711 should be reset once by bringing the pdn pin = ?l? after all power supplies are supplied. note 18. i 2 c-bus is a trademark of nxp b.v.
[ak4711] rev. 0.4 2011/07 - 12 - timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn power-down timing
[ak4711] rev. 0.4 2011/07 - 13 - operation overview 1. system reset and power-down options the ak4711 should be reset once by bringing the pdn pin = ?l? after all power supplies are supplied. the ak4711 has several operation modes. the pdn pin and mu te bit control operation mode as shown in table 2 and table 3 . system reset and full power-down mode the ak4711 should be reset once by bringing the pdn pin = ?l? after all power supplies are supplied. pdn pin: power down pin l: full power-down mode. power-down, reset and initializes control registers. h: device active. mute mode when the mute bit = ?1?, the audio outputs settle to vss(0v, typ) and the charge pump circuit is in power down mode. mute bit (00h d1): audio output control 0: normal operation. 1: all audio outputs to gnd (default) mode pdn pin mute bit mode 0 l x full power-down 1 h 1 mute ( note 19 ) (amp power down) 2 h 0 normal operation (amp operation) note 19. tvoutl/r are muted by mute bit in the default state. table 2. operation mode settings (x: don?t care) mode register control audio charge pump video output tvfb tvsb power consumption (typ.) ( note 20 ) 0 full power-down not available hi-z pull -down ( note 21 ) 0.6mw no video input hi-z 1.86mw 1 mute (amp power down) video input hi-z/ active 228mw no video input power down hi-z 1.86mw 2 normal operation (amp operation) video input available active hi-z/ active active active 250mw note 20. 1khz 2vrms output with 4.5k : load at all audio output pins. 47.46 ire at all video inputs corresponding to all video output pins with 150 : load. note 21. internally pulled down by 120k : (typ) resistor. table 3. status of each operation modes
[ak4711] rev. 0.4 2011/07 - 14 - normal operation mode to change analog switches, set the mu te bit to ?0?. the ak4710/11 is in powe r-down mode until the pdn pin = ?h?. the figure x shows an example of the system timing at the power-down and power-up by the pdn pin. typical operation sequence figure 2 shows an example of the system timing at normal operation mode. pdn p in ?1? (default) mute bit ?0? ?1? ?0? ?mute? tvout analog in ?1? charge pump ?normal? ?normal? analog in 50ms(max) (note21) video detect video signal signal in no signal no signal 175ms(max) video output hi-z active hi-z (note21) (gnd) 50ms(max) note 22. mute the analog outputs externally if click noise affects the system. figure 2 . typical operating sequence
[ak4711] rev. 0.4 2011/07 - 15 - 2. audio block volume control (11-level volume) the ak4711 has an 11-level volume control as shown in table 4 . the volume reflects the ch ange of register value immediately. figure 3. volume (volume gain=0db: default), full differential stereo input (0dh: d6-d3) vol3 vol2 vol1 vol0 volume ga in output level (typ) 1 1 x x -- reserved 1 0 1 1 +24db 2vrms (with 0.13vrms differential input) 1 0 1 0 +21db - 1 0 0 1 +18db 2vrms (with 0.25vrms differential input) 1 0 0 0 +15db - 0 1 1 1 +12db 2vrms (with 0.5vrms differential input) 0 1 1 0 +9db - 0 1 0 1 +6db 2vrms (with 1vrms differential input) 0 1 0 0 +3db - 0 0 1 1 0db 2vrms (with 2vrms differential input: default) 0 0 1 0 -3db - 0 0 0 1 -6db 1vrms (with 2vrms differential input) 0 0 0 0 mute - (x : don?t care) table 4. volume, full differential stereo input figure 4. volume (volume gain=0db:default), single-ended input 2vrms differential input tvoutl/r ainl/r+ ainl/r- volume gain 0db vo lum e 1vrms 1vrms 2vrms 0.47 0.47 300 300 ainl/r+ a inl/r- tvoutl/r vo lume ga in 0 db volume 2vrms 2vrms 0.47 0.47 300 300
[ak4711] rev. 0.4 2011/07 - 16 - (0dh: d6-d3) vol3 vol2 vol1 vol0 volume ga in output level (typ) 1 1 x x -- reserved 1 0 1 1 +24db 2vrms (with 0.13vrms input) 1 0 1 0 +21db - 1 0 0 1 +18db 2vrms (with 0.25vrms input) 1 0 0 0 +15db - 0 1 1 1 +12db 2vrms (with 0.5vrms input) 0 1 1 0 +9db - 0 1 0 1 +6db 2vrms (with 1vrms input) 0 1 0 0 +3db - 0 0 1 1 0db 2vrms (with 2vrms input: default) 0 0 1 0 -3db - 0 0 0 1 -6db 1vrms (with 2vrms input) 0 0 0 0 mute - (x: don?t care) table 5. volume, single-ended input
[ak4711] rev. 0.4 2011/07 - 17 - analog output block the ak4711 has a charge pump circuit generating negativ e power supply rail from a 3.3v(typ) power supply. ( figure 5 ) it allows the ak4711 to output audio signal centered at vss (0v, typ) as shown in figure 6 . the negative power generating circuit ( figure 5 ) needs 1.0uf capacitors (ca, cb) with low es r (equivalent series resistance). when using capacitors with a polarity, the positive side should be connected to cp and vss2 for capacito r ca and cb, respectively. when the mute bit = ?1?, the charge pump circuit is in power down mode and its analog outputs become vss (0v, typ). vd charge pump cp cn vss2 vee 1uf 1uf negative power a k4711 (+) cb ca (+) figure 5. negative power generate circuit tvoutr/tvoutl a k 4 711 0v 2vrms figure 6. audio signal output
[ak4711] rev. 0.4 2011/07 - 18 - 3. video block video switch control the ak4711 has switches for tv. each switch can be controlled via the re gisters independently. (04h: d1-d0) mode vtv1-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown (default) 00 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs+rgb or encoder ypbpr 01 encv pin (encoder cvbs or y) encrc pin (encoder red,c or pb) encg pin (encoder green or y) encb pin (encoder blue or pr) encoder y/c 1 10 encv pin (encoder y) encrc pin (encoder c) (hi-z) (hi-z) encoder y/c 2 11 ency pin (encoder y) encc pin (encoder c) (hi-z) (hi-z) table 6. tv video output ( note 23 ) (04h: d4-d3) mode rca1-0 bit source of rcavout pin shutdown(default) 00 (hi-z) encoder cvbs 01 encv pin encoder cvbs 10 ency pin (reserved) 11 - table 7. rca video output ( note 23 ) note 23. when input video signals via the encrc pin, set clamp1-0 bits respectively.
[ak4711] rev. 0.4 2011/07 - 19 - video output control (05h: d6-d0) each video output can be set to hi-z i ndividually via the c ontrol registers. tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control rcav: rcavout output control tvfb: tvfb output control 0: hi-z. (default) 1: active. clamp and dc-restore circuit control (06h: d7-d3) each cvbs and y input has a sync tip clamp circuit. the dc-restore circuit has two cl amp voltages; 0.20v(typ) and 1.44v(typ) to support both rgb and yp bpr signal. they correspond to 0.10v (typ) and 0.72v(typ) at the scart connector when matched by 75 resistors. clamp1 and clampb bits sel ect the input circuit for both the encrc pin (encoder red/chroma) and the encb pin (e ncoder blue), and clamp2 bit selects the input circuit for the encg pin. vclp1-0 bits select the sync s ource of dc- restore circuit. clampb clamp1 encrc input circ uit encb input circuit note 0 0 dc restore clamp active (0.20v at sync timing/output pin) dc restore clamp active (0.20v at sync timing/output pin) for rgb (default) 0 1 biased (1.44v at sync timing/output pin) dc restore clamp active (0.20v at sync timing output pin) for y/c 1 0 dc restore clamp active (1.44v at sync timing/output pin) dc restore clamp active (1.44v at sync timing/output pin) for y/pb/pr 1 1 (reserved) (reserved) table 8. dc-restore c ontrol for encoder input clamp2 encg input circuit note 0 dc restore clamp active (0.20v at sync timing/output pin) for rgb (default) 1 sync tip clamp active (0.20v at sync timing/output pin) for y/pb/pr note: when the vtv1-0 bits = ?01? (source for tv = en coder cvbs /rgb), tvg bit = ?1? (tvg = active) and vclp1-0 bits = ?11? (dc restore source = encg), the sync tip is selected even if the clamp2 bit = ?0?. table 9. dc-restore control for encoder green/y input vclp1-0: dc restore source control vclp1 vclp0 sync source of dc restore 0 0 encv (default) 0 1 ency 1 0 (reserved) 1 1 encg table 10. dc-restore source control
[ak4711] rev. 0.4 2011/07 - 20 - hd video control (0ah: d7-d6) fly1/0, flpb1/0, flpr1/0 bits a nd hdcp1/0, hdy1/0 bits set the hd video switch and filter response. hdcp1 hdcp0 hd pbpr ? rgb control 0(default) 0(default) ypbpr. y = 0.2v clamp, encb = 1.44v dc-restore, encrc = 1.44v dc-restore. (y= sync source only for encpb, encpr) 1 0 rgb. y = 0.2v clamp, encb = 0.2v dc-restore, encrc = 0.2v dc-restore. (y= sync source only for encpb, encpr) 1 1 rgb. y = 0.2v dc-restore, encb = 0.2v dc-restore, encrc = 0.2v dc-restore. sync source = encv 0 1 hi-z table 11. hd video switch control (3ch common) hdy1 hdy0 y input control 0 0 encg(default) 0 1 encv 1 0 ency 1 1 (reserved) table 12. hd video switch control (3ch common) input output fly1/ flpb1/flpr1 bit fly0/ flpb0/flpr0 bit lfp response 0 0 6mhz lpf (default) 0 1 12mhz lpf 1 0 30mhz lpf 1 1 (reserved) table 13. hd video filter control (3ch independent)
[ak4711] rev. 0.4 2011/07 - 21 - 4. blanking control the ak4711 supports fast blanking signa ls and slow blanking (function switching) signals for tv scart. input/output control for fast/slow blanking fb: tv fast blanking out put control (07h: d1-d0) input output fb1 bit fb0 bit tvfb pin output level 0 0 0v (default) 0 1 2v<, 2.5v(typ) at 150 load 1 0 (reserved) 1 1 (reserved) table 14. tv fast blanking out put (note: minimum load is 150 ) sbt1-0: tv slow blanking output control (07h: d3-d2) input output sbt1 bit sbt0 bit tvsb pin output level 0 0 <2v (default) 0 1 4.73v <, < 7v 1 0 (reserved) 1 1 10v< table 15. tv slow blanking out put (note: minimum load is 10k )
[ak4711] rev. 0.4 2011/07 - 22 - 5. control interface (i 2 c-bus control) 1. write operations figure 7 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while sc l is high indicates a start condition ( figure 13 ). after the start condition, a slave address is sent. this a ddress is 7bits long followed by the eighth b it that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the ak4711, the ak4711 generates the acknowledge and the opera tion is executed. the master must generate the acknowledge-related clock pul se and release the sda line (high) during the acknowledge clock pulse ( figure 15 ). a ?1? for r/w bit indicates that the read operation is to be ex ecuted. a ?0? indicates that the write operation is to be executed. the second byte consists of th e address for control registers of the ak4711. the format is msb first, and those most significant 3-bits are fixed to zeros ( figure 9 ). the data after the second byte contain control data. the format is msb first, 8bits ( figure 10 ). the ak4711 generates an acknowledge after each by te has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 13 ). the ak4711 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the ak4711 generates an acknowledge, and awaits the next data again. the master can tr ansmit more than one byte instead of terminating the write cycle after the first data byte is tr ansferred. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 0dh prior to generating the stop condition, the addre ss counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high pe riod of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low ( figure 15 ) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 7. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 8. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 9. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 10. byte structure after the second byte
[ak4711] rev. 0.4 2011/07 - 23 - 2. read operations set r/w bit = ?1? for read operations. after transmission of da ta, the master can read the next address?s data by generating an acknowledge instead of termina ting the write cycle after the receipt th e first data word. after the receipt of each data, the internal address counter is incremented by one, a nd the next data is taken into next address automatically. if the address exceeds 09h prior to generati ng the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the ak4711 supports two basic read operations : current address read and random read. 2-1. current address read the ak4711 contains an internal address counter that mainta ins the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the ak4711 generates an acknowledge, transmits 1byte data which address is set by th e internal address counter and increments the internal address counter by 1. if the master does not ge nerate an acknowledge to the data but generate the stop condition, the ak4711 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 11. current address read 2-2. random read random read operation allows the master to access any mem ory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write ope ration. the master issues a start condition, slave address (r/w bit = ?0?) and then th e register address to read. after the re gister address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit se t to ?1?. then the ak4711 generates an acknowledge, 1-byte data and increments the internal addre ss counter by 1. if the mast er does not generate an acknowledge to the data but generate the stop condition, the ak4711 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 12. random address read
[ak4711] rev. 0.4 2011/07 - 24 - scl sda stop condition start condition s p figure 13. start a nd stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 14. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 15. bit transfer on the i 2 c-bus
[ak4711] rev. 0.4 2011/07 - 25 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 1 0 mute 1 01h switch 1 0 0 1 mono 1 0 1 02h reserve 0 0 0 0 0 0 0 0 03h zerocross 0 0 cal 0 0 1 1 1 04h video switch 0 0 0 rca1 rca0 1 vtv1 vtv0 05h video output enable 0 tvfb 0 rcav tvb tvg tvr tvv 06h video volume/clamp clampb vclp1 vclp0 clamp2 clamp1 1 0 0 07h s/f blanking control 0 0 0 0 sbt1 sbt0 fb1 fb0 08h reserve 0 0 0 0 0 0 0 0 09h reserve 0 0 0 0 0 0 0 0 0ah hd switch hdcp1 hdcp0 hdapw 0 0 0 1 1 0bh hd filter 0 0 flpr1 flpr0 flpb1 flpb0 fly1 fly0 0ch sync filter 0 flt 0 0 0 0 0 0 0dh volume 0 vol3 vol2 vol1 vol0 1 1 1 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin = ?h?, all registers can be accessed. do not write any data to the register over 0dh. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 1 0 mute 1 r/w r/w default 0 0 0 0 1 0 1 1 mute: audio output control 0: normal operation 1: all audio outputs to gnd (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch 1 0 0 1 mono 1 0 1 r/w r/w default 1 0 0 1 0 1 0 1 mono: mono select for tvoutl/r pins 0: stereo. (default) 1: mono. (l+r)/2
[ak4711] rev. 0.4 2011/07 - 26 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h volume control 0 0 cal 0 0 1 1 1 r/w r/w default 0 0 1 0 0 1 1 1 cal: offset calibration enable 0: offset calibration disable. 1: offset calibration enable (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch 0 0 0 rca1 rca0 1 vtv1 vtv0 r/w r/w default 0 0 0 1 1 1 0 0 vtv1-0: selector for tv video output refer to table 6 . rca1-0: selector for rca video output refer to table 7 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable 0 tvfb 0 rcav tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout out put control tvr: tvrcout output control tvg: tvgout out put control tvb: tvbout output control rcav: rcavout out put control tvfb: tvfb output control 0: hi-z (default) 1: active. addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume clampb vclp1 vclp0 clamp2 clamp1 1 0 0 r/w r/w default 0 0 0 0 0 1 0 0 clampb, clamp2-1: clamp control. refer to table 8 and table 9 . vclp1-0: dc restore source control 00: encv pin (default) 01: ency pin 10: (reserved) 11: encg pin
[ak4711] rev. 0.4 2011/07 - 27 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking 0 0 0 0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking out put control (for tvfb pin) 00: 0v (default) 01: 2v<, 2.5v(typ) at 150 load 10: (reserved) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pi n. minimum load is 10k .) 00: < 2v (default) 01: 4.73v <, < 7v 10: (reserved) 11: 10v < addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah hd switch hdcp1 hdcp0 hdapw 0 0 0 1 1 r/w r/w default 0 0 0 0 0 0 1 1 hdapw: hd filter power-up bit(hd video output) 1: hd filter power-up. 0: hd filter power-down (default). hdcp1-0: hd video switch control refer to table 11 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh hd filter hdy1 hdy0 flpr1 flpr0 flpb1 flpb0 fly1 fly0 r/w r/w default 0 0 0 0 0 0 0 0 hdy1-0: y input control refer to table 12 . fly1-0, flpb1-0, flpr1-0: hd video filter control refer to table 13 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch sync filter 0 flt 0 0 0 0 0 0 r/w r/w default 0 0 0 0 0 0 0 0 flt: hd sync detecti on filter (500khz band-width) 1: filter on in all case 0: filter off when hd path is used (default).
[ak4711] rev. 0.4 2011/07 - 28 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh main volume 0 vol3 vol2 vol1 vol0 1 1 1 r/w r/w default 0 0 0 1 1 1 1 1 vol3-0: volume control those registers control bot h lch and rch of volume. 1011: volume gain = +24db 1010: volume gain = +21db 1001: volume gain = +18db 1000: volume gain = +15db 0111: volume gain = +12db 0110: volume gain = +9db 0101: volume gain = +6db 0100: volume gain = +3db 0011: volume gain = +0db (default) 0010: volume gain = -3db 0001: volume gain = -6db 0000: mute
[ak4711] rev. 0.4 2011/07 - 29 - system design figure 16 shows the system connection diagram example. an evaluation board (akd4711) de monstrates application circuits, the optimum layout, power suppl y arrangements and measurement results. hdvvd 1 tvrc 2 hdpr 3 hdrb 4 racvout 5 vss3 6 7 tvvout 8 tvfb 9 tvg pdn vss2 cp cn vee 13 14 15 16 17 18 19 20 21 ak4711 tvb vvd encb encg enrc encc encv ency vp 26 25 24 23 22 21 20 19 27 ainr+ ainr- vd1 vss1 tvsb tvoutl tvoutr ainl- 36 35 34 33 32 31 30 29 28 75 75 video 3.3v video encoder 0.1u 75 mpeg micro controller a udio 3.3v decoder dacl dacr analog 12v tv scart 0.1u 0.1u 0.1u 75 75 75 75 a nalog ground digital ground ainl+ 0.1u hdy 75 sd a scl vd2 4.7u + analog 3.3v 1.0u 1.0u 10 300 300 0.1u 1u + 0.47u 300 0.47u 300 0.47u 300 0.47u 300 470 0.1u 0.1u 75 75 analog 3.3 v 75 75 75 75 cinch video hd video 75 analog 3.3v 0.1u 4.7u 0.1u 4.7u + + + 4.7u 0.1u figure 16. typical connection diagram
[ak4711] rev. 0.4 2011/07 - 30 - grounding and power supply decoupling vd1, vd2, vp, vvd, vss1, vss2 and vss3 should be supp lied from analog supply unit with low impedance and be separated from system digital suppl y. an electrolytic capacitor 4.7 f parallel with a 0.1 f ceramic capacitor should be attached to vd1, vd2, vvd, vss1, vss2 and vss3 pin to eliminate the effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as n ear to vd1 (vd2, vvd) as possible. the vp pin must be connected to the analogue 12v pow er supply via a 10ohm resistor and with a 0.1f ceramic capacitor in parallel with a 1f electrol ytic capacitor to vss1, as shown in figure 16 . analog audio outputs the analog outputs are also single-ende d and centered on 0v(typ.). the output signal range is typically 2vrms . slow blanking pins the slow blanking pin must have a 470ohm 5% series resistor.
[ak4711] rev. 0.4 2011/07 - 31 - external circuit example the analog audio input pin must have 300ohm series re sistor and 0.47uf capacitor. analog audio input pin ainr+ ainr- ainl+ ainl- 0.47 f 300 : analog audio output pin tvoutl/r 300 : to t al > 4. 5 k : (cable) analog video input pin encv, ency, encrc, encc, encg, encb, 0.1 f 75 : (cable) 75 : analog video output pin tvvout, tvrc tvg,tvr,tvb, rcavout, hdy, hdpr, hdpb max 400pf 75 : 75 : max 15pf (cable)
[ak4711] rev. 0.4 2011/07 - 32 - slow blanking pin tvsb max 3nf (with 470 ) 470 5% min: 10k (cable) fast blanking output pin tvfb 75 75 (cable)
[ak4711] rev. 0.4 2011/07 - 33 - package 36pin qfn (unit: mm) a b 5.00 0.10 5.00 0.10 c0.35 0.20 0.05 #1 #9 #10 #18 #19 #27 #28 #36 0.28 0.10 0.28 0.10 0.35 0.1 0.75 0.05 0.20 0.40 s 0.10 s top view bottom view 0.08 s 0.07 m s a b 1.30 0.90 0.90 1.30 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4711] rev. 0.4 2011/07 - 34 - marking 4711 xxxx 1 xxxx : date code (4 digit) pin #1 indication important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these products , please make inquiries the sales office of asahi kasei microdevices corporation (akm) or au thorized distributors as to current status of the products. z descriptions of external circuits, app lication circuits, software and other related informa tion contained in this document are provided only to illustrate the operation and application examples of th e semiconductor products. you are fully responsible for the incorporation of these external circ uits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other right s in the application or use of su ch information c ontained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to cu stoms and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by re presentative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very hi gh standards of performance and reliability. note2 ) a hazard related device or system is one designe d or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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